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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 features footprint compatible with wed3c750a8m-200bx footprint compatible with motorola mpc 745 risc microprocessor multichip package overview the wedc 755/ssram multichip package is targeted for high performance, space sensitive, low power systems and supports the following power management features: doze, nap, sleep and dynamic power management. the wed3c7558m-xbx multichip package consists of: 755 risc processor dedicated 1mb ssram l2 cache, con? gured as 128kx72 21mmx25mm, 255 ceramic ball grid array (cbga) core frequency/l2 cache frequency (300mhz/ 150mhz, 350mhz/175mhz) maximum 60x bus frequency = 66mhz the wed3c7558m-xbx is offered in commercial (0c to +70c), industrial (-40c to +85c) and military (-55c to +125c) temperature ranges and is well suited for embedded applications such as missiles, aerospace, ? ight computers, ? re control systems and rugged critical systems. * this product is subject to change without notice. figure 1 C multi-chip package diagram
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 figure 2 C block diagram
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 figure 3 C block diagram, l2 interconnect l2pin_data l2pin_data l2pin_data l2pin_data l2 clk_out a l2we# l2ce# a0-16 l2clk_out b l2pin_data l2pin_data l2pin_data l2pin_data l2zz p 755 dqa dqb dqc dqd k sgw# se1# sa0-16 sa0-16 sgw# se1# k dqa dqb dqc dqd ssram 1 ssram 2 ft# sbd# sbc# sbb# sba# sw# adsp# adv# se2 adsc# se3# lbo# g# ft# sbd# sbc# sbb# sba# sw# adsp# adv# se2 adsc# se3# lbo# g# l20v cc l20v cc l2dp0-3 dp0-3 l2dp4-7 dp0-3 zz zz u2 u1 figure 4 C block diagram, l2 interconnect l2 cache ssram u2 l2 cache ssram u1 stdo stdi stms stck tdi tdo 755 tms tck trst
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 figure 5 C pin assignments ball assignments of the 255 cbga package as viewed from the top surface. side pro? le of the cbga package to indicate the direction of the top surface view.
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 package pinout listing signal name pin number active i/o 2.0v (7) 3.3v (7) a[0-31] c16, e4, d13, f2, d14, g1, d15, e2, d16, d4, e13, g2, e15, h1, e16, h2, f13, j1, f14, j2, f15, h3, f16, f4, g13, k1, g15, k2, h16, m1, j15, p1 high i/o aack# l2 low input abb# k4 low i/o ap[0-3] c1, b4, b3, b2 high i/o artry# j4 low i/o av cc a10 2.0v 2.0v bg# l1 low input br# b6 low output bvsel (4, 5, 6) b1 high input gnd 3.3v ci# e1 low output ckstp_in# d8 low input ckstp_out# a6 low ouput clk_out d7 output dbb# j14 low i/o dbg# n1 low input dbdis# h15 low input dbwo# g4 low input dh[0-31] p14, t16, r15, t15, r13, r12, p11, n11, r11, t12, t11, r10, p9, n9, t10, r9, t9, p8, n8, r8, t8, n7, r7, t7, p6, n6, r6, t6, r5, n5, t5, t4 high i/o dl[0-31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n12, t13, p3, n3, n4, r3, t1, t2, p4, t3, r4 high i/o dp[0-7] m2, l3, n2, l4, r1, p2, m4, r2 high i/o drtry# g16 low input gbl# f1 low i/o gnd c5, c12, e3, e6, e8, e9, e11, e14, f5, f7, f10, f12, g6, g8, g9, g11, h5, h7, h10, h12, j5, j7, j10, j12, k6, k8, k9, k11, l5, l7, l10, l12, m3, m6, m8, m9, m11, m14, p5, p12 gnd gnd hreset# a7 low input int# b15 low input l1_tstclk (1) d11 high input l2_tstclk (1) d12 high input l2av cc (8) l11 2.0v 2.0v l2ov cc (9) e10, e12, m12, g12, g14, k12, k14 2.0v 3.3v l2vsel (4, 5, 6, 7) b5 high input * 3.3v lssd_mode# (1) b10 low input mcp# c13 low input nc (no-connect) c3, c6, d5, d6, h4, a4, a5, a2, a3 ov cc (2) c7, e5, g3, g5, k3, k5, p7, p10, e7, m5, m7, m10 pll_cfg[0-3] a8, b9, a9, d9 high input qack# d3 low input qreq# j3 low output rsrv# d1 low output smi# a16 low input sreset# b14 low input stck (10) b7 input stdi c8 input stdo j16 output * not supported on this version
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 package pinout listing (continued) signal name pin number active i/o 2.0v (7) 3.3v (7) stms b8 input sysclk c9 input ta# h14 low input tben c2 high input tbst# a14 low i/o tck c11 high input tdi (6) a11 high input tdo a12 high output tea# h13 low input tlbisync# c4 low input tms (6) b11 high input trst# (6) c10 low input ts# j13 low i/o tsiz[0-2] a13, d10, b12 high output tt[0-4] b13, a15, b16, c14, c15 high i/o wt d2 low output v cc (2) f6, f8, f9, f11, g7, g10, h6, h8, h9, h11, j6, j8, j9, j11, k7, k10, l6, l8, l9 2.0v 2.0v voldet (3) f3 low output notes: 1. these are test signals for factory use only and must be pulled up to ov cc for normal machine operation. 2. ov cc inputs supply power to the i/o drivers and v cc inputs supply power to the processor core. 3. internally tied to gnd in the bga package to indicate to the power supply that a low-voltage processor is present. this signal is not a power supply pin. 4. to allow processor bus i/0 voltage changes, provide the option to connect bvsel and l2vsel independently to either ov cc (selects 3.3v interface) or to gnd (selects 2.0v interface). 5. uses one of 15 existing no-connects in wedcs wed3c750a8m-200bx. 6. internal pull up on die. 7. ov cc supplies power to the processor bus, jtag, and all control signals except the l2 cache controls (l2ce, l2we, and l2zz); l2ov cc supplies power to the l2 cache i/o interface (l2addr (0-16], l2data (0-63), l2dp{0-7] and l2sync-out) and the l2 control signals and the ssram power supplies; and v cc supplies power to the processor core and the pll and dll (after ? ltering to become av cc and l2av cc respectively). these columns serve as a reference for the nominal voltage supported on a given signal as selected by the bvsel/l2vsel pin con? gurations and the voltage supplied. for actual recommended value of vin or supply voltages see recommended operating conditions. 8. uses one of 20 existing v cc pins in wedc's wed3c750a8m-200bx, no board level design changes are necessary. for new designs of wed3c7558m-xbx refer to pll power supply ? ltering. 9. l20v cc for future designs that will require 2.0v l2 cache power supply - compatible with existing design using wed3c750a8m-200bx. 10. to disable ssram tap controllers without interfering with the normal operation of the devices, stck should be tied low (gnd) to prevent clocking the devices. 11. stdi and stms are internally pulled up and may be left unconnected. upon power-up the ssram devices will come up in a reset state which will not interfere with the operation of the device.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 recommended operating conditions characteristic symbol recommended value unit core supply voltage v cc 2.0 100mv v pll supply voltage av cc 2.0 100mv v l2 dll supply voltage l2av cc 2.0 100mv v processor bus supply voltage bvsel = 0 ov cc 2.0 100mv v bvsel = 1 ov cc 3.3 165mv v l2 bus supply voltage l2vsel = 1 l20v cc 3.3 165mv v input voltage processor bus v in gnd to ov cc v jtag signals v in gnd to ov cc v note: these are the recommended and tested operating conditions. proper device operation outside of these conditions is not gu aranteed. absolute maximum ratings characteristic symbol value unit notes core supply voltage v cc -0.3 to 2.5 v (4) pll supply voltage av cc -0.3 to 2.5 v (4) l2 dll supply voltage l2av cc -0.3 to 2.5 v (4) 60x bus supply voltage ov cc -0.3 to 3.465 v (3) l2 bus supply voltage l2ov cc -0.3 to 3.465 v (3) input supply processor bus v in -0.3 to 0v cc +0.3 v (2) l2 bus v in -0.3 to l20v cc +0.3 v (2) jtag signals v in -0.3 to 3.6 v (2) storage temperature range t stg -55 to 150 c notes: 1. functional and tested operating conditions are given in operating conditions table. absolute maximum ratings are stress rati ngs only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: vin must not exceed ov cc by more than 0.3v at any time including during power-on reset. 3. caution: ov cc /l2ov cc must not exceed v cc /av cc /l2av cc by more than 1.6 v at any time including during power-on reset. 4. caution: v cc /av cc /l2av cc must not exceed l2ov cc /ov cc by more than 0.4 v at any time including during power-on reset.
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 power consumption v cc = av cc = 2.0 0.1v vdc, ov cc = 3.3v 5% vdc, gnd = 0 vdc, 0 t j < 105c processor (cpu) frequency/l2 frequency unit notes 300/150 mhz 350/175mhz full-on mode typical 4.1 4.6 w 1, 3 maximum 6.7 7.9 w 1, 2 doze mode maximum 2.5 2.8 w 1, 2 nap mode maximum 1700 1800 mw 1, 2 sleep mode maximum 1200 1300 mw 1, 2 sleep modeCpll and dll disabled maximum 500 500 mw 1, 2 notes: 1. these values apply for all valid 60x bus and l2 bus ratios. the values do not include ov cc ; av cc and l2av cc suppling power. ov cc power is system dependent, but is typically <10% of v cc power. worst case power consumption, for av cc =15mw and l2av cc =15mw. 2. maximum power is measured at v cc =2.1v while running an entirely cache-resident, contrived sequence of instructions which keep the execution units maximally bus y. 3. typical power is an average value measured at v cc =av cc =l2av cc =2.0v, ov cc =l2ov cc =3.3v in a system, executing typical applications and benchmark sequences. l2 cache control register (l2cr) the l2 cache control register, shown in figure 5, is a supervisor-level, implementation-speci? c spr used to con? gure and operate the l2 cache. it is cleared by hard reset or power-on reset. the l2cr bits are described in table 1. figure 5 C l2 cache control register (l2cr) l2e l2siz l2clk l2ram l2i l20h 0 0 l2ctr 0 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 30 31 l2pe l2do l2ctl l2ts l2sl l2byp l2io l2dro l2ip l2wt l2df l2cs reserved
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 table 1: l2cr bit settings bit name function 0 l2e l2 enable. enables l2 cache operation (including snooping) starting with the next transaction the l2 cache unit receives. before enabling the l2 cache, the l2 clock must be con? gured through l2cr[2clk], and the l2 dll must stabilize. all other l2cr bits must be set appropriately. the l2 cache may need to be invalidated globally. 1 l2pe l2 data parity checking enable. enables parity generation and checking for the l2 data ram interface. when disabled, gener ated parity is always zeros. l2 parity is supported by wedcs wed3c7558m-xbx, but is dependent on application. 2C3 l2siz l2 size should be set according to the size of the l2 data rams used. 11 1 mbyte - setting for wed3c7558m-xbx 4C6 l2clk l2 clock ratio (core-to-l2 frequency divider). speci? es the clock divider ratio based from the core clock frequency th at the l2 data ram interface is to operate at. when these bits are cleared, the l2 clock is stopped and the on-chip dll for the l2 interface i s disabled. for nonzero values, the processor generates the l2 clock and the on-chip dll is enabled. after the l2 clock ratio is chosen, the dll must stabilize before the l2 interface can be enabled. the resulting l2 clock frequency cannot be slower than the clock frequency of the 60x bus interface. 000 l2 clock and dll disabled 001 1 010 1.5 011 reserved 100 2 101 2.5 110 3 111 reserved 7C8 l2ram l2 ram type con? gures the l2 ram interface for the type of synchronous srams used: ? pipelined (register-register) synchronous burst srams that clock addresses in and clock data out the 755 does not burst data into the l2 cache, it generates an address for each access. 10 pipelined (register-register) synchronous burst sram C setting for wed3c7558m-xbx 9 l2do l2 data only. setting this bit enables data-only operation in the l2 cache. for this operation, instruction transactions f rom the l1 instruction cache already cached in the l2 cache can hit in the l2, but new instruction transactions from the l1 instruction ca che are treated as cache-inhibited (bypass l2 cache, no l2 checking done). when both l2do adn l2io are set, the l2 cache is effectively locked (cache misses do not cause new entries to be allocated but write hits use the l2). 10 l2i l2 global invalidate. setting l2i invalidates the l2 cache globally by clearing the l2 status bits. this bit must not be s et while the l2 cache is enabled. see motorolas user manual for l2 invalidation procedure. 11 l2ctl l2 ram control (zz enable). setting l2ctl enables the automatic operation of the l2zz (low-power mode) signal for cache rams. sleep mode is supported by the wed3c7558m-xbx . while l2ctl is asserted, l2zz asserts automatically when the device enters nap or sleep mode and negates automatically when the device exits nap or sleep mode. this bit should not be set when the device is in nap mode and snooping is to be performed through deassertion of qack#. 12 l2wt l2 write-through. setting l2wt selects write-through mode (rather than the default write-back mode) so all writes to the l2 cache also write through to the system bus. for these writes, the l2 cache entry is always marked as exclusive rather than modi? ed. this bit must never be asserted after the l2 cache has been enabled as previously-modi? ed lines can get remarked as exclusive during normal operation. 13 l2ts l2 test support. setting l2ts causes cache block pushes from the l1 data cache that result from dcbf and dcbst instructions to be written only into the l2 cache and marked valid, rather than being written only to the system bus and marked invalid in the l2 cache in case of hit. this bit allows a dcbz/dcbf instruction sequence to be used with the l1 cache enabled to easily initialize the l2 cache with any address and data information. this bit also keeps dcbz instructions from being broadcast on the system and single-beat cacheable store misses in the l2 from being written to the system bus. 0: setting for the l2 test support as this bit is reserved for tests. 14C15 l2oh l2 output hold. these bits con? gure output hold time for address, data, and control signals driven to the l2 data ram s. 00: least hold time C setting for wed3c7558m-xbx
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 table 1: l2cr bit settings bit name function 16 l2sl l2 dll slow. setting l2sl increases the delay of each tap of the dll delay line. it is intended to increase the delay thr ough the dll to accommodate slower l2 ram bus frequencies. 0: setting for wed3c7558m-xbx because l2 ram interface is operated above 100 mhz. 17 l2df l2 differential clock. this mode supports the differential clock requirements of late-write srams. 0: setting for wed3c7558m-xbx because late-write srams are not used. 18 l2byp l2 dll bypass is reserved. 0: setting for wed3c7558m-xbx 19-20 reserved. these bits are implemented but not used; keep at 0 for future compatibility. 21 l2io l2 instruction-only. setting this bit enables instruction-only operation in the l2 cache. for this operation, data transa ctions from the l1 data cache already cached in the l2 cache can hit in the l2 (including writes), but new data transactions (transactions that mi ss in the l2) from the l1 data cashe are treated as cache-inhibited (bypass l2 cache, no l2 checking done). when both l2do and l2io are set, the l2 cache is effectively locked (cache misses do not cause new entries to be allocated but write hits use the l2). note that this bit can be programmed dynamically. 22 l2cs l2 clock stop. setting this bit causes the l2 clocks to the srams to automatically stop whenever the mpc755 enters nap or sleep modes, and automatically restart when exiting those modes (including for snooping during nap mode). it operates by asynchronous ly gating off the l2clk_out [a:b] signals while in nap or sleep mode. the l2sync_out/sync_in path remains in operation, keeping the dll synchronized. this bit is provided as a power-saving alternative to the l2ctl bit and its corresponding zz pin, which m ay not be useful for dynamic stopping/restarting of the l2 interface from nap and sleep modes due to the relatively long recovery time from zz negation that the sram requires. 23 l2dro l2 dll rollover. setting this bit enables a potential rollover (or actual rollover) condition of the dll to cause a chec kstop for the processor. a potential rollover condition occurs when the dll is selecting the last tap of the delay line, and thus may risk ro lling over to the ? rst tap with one adjustment while in the process of keeping synchronized. such a condition is improper operation for t he dll, and, while this condition is not expected, it allows detection for added security. this bit can be set when the dll is ? rst en abled (set with the l2clk bits) to detect rollover during initial synchronization. it could also be set when the l2 cache is enabled (with l2e bit) after the dll has achieved its initial lock. 24C30 l2ctr l2 dll counter (read-only). these bits indicate the current value of the dll counter (0 to 127). they are asynchronou sly read when the l2cr is read, and as such should be read at least twice with the same value in case the value is asynchronously caught in transition. these bits are intended to provide observability of where in the 128-bit delay chain the dll is at any given time. generally, the dll operation should be considered at risk if it is found to be within a couple of taps of its beginning or end point (tap 0 or tap 128). 31 l2ip l2 global invalidate in progress (read only)see the motorola users manual for l2 invalidation procedure.
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 the av cc and l2av cc power signals are provided on the wed3c7558m-xbx to provide power to the clock generation phase-locked loop and l2 cache delay-locked loop respectively. to ensure stability of the internal clock, the power supplied to the av cc input signal should be ? ltered of any noise in the 500khz to 10 mhz resonant frequency range of the pll. a circuit similar to the one shown in figure 6 using surface mount capacitors with minimum effective series inductance (esl) is recommended. multiple small capacitors of equal value pll power supply filtering are recommended over a single large value capacitor. the circuit should be placed as close as possible to the av cc pin to minimize noise coupled from nearby circuits. an identical but separate circuit should be placed as close as possible to the l2av cc pin. it is often possible to route directly from the capacitors to the av cc pin, which is on the periphery of the 255 bga footprint, without the inductance of vias. the l2av cc pin may be more dif? cult to route but is proportionately less critical. figure 6 C power supply filter circuit avcc (or l2avcc) 2.2 f 2.2 f gnd low esl surface mount capacitors vcc 10 ?
12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 package outline 21x25mm interconnects 255 (16x16 ball array less one) pitch 1.27mm maximum module height 3.90mm ball diameter 0.8mm package dimensions 255 ball grid array package description notes: 1. dimensions in millimeters and paranthetically in inches. 2. a1 corner is designated with a ball missing the array. t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bottom view top view
13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed3c7558m-xbx august 2002 rev. 7 wed 3 c 755 8m x b x device grade: m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package type: b = 255 ceramic ball grid array core frequency (mhz) 350 = 350mhz/175mhz l2 cache 300 = 300mhz/150mhz l2 cache l2 cache density: 8mbits = 128k x 72 ssram powerpc ? : type 755 (d - die revision) c = multichip package 3 = powerpc ? white electronic designs corp. ordering information powerpc ? is a trademark of international business machine corp.

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